1. Field of the Invention
The present invention relates to the field of hypertransport-based switching and more particularly to hypertransport switching multiple central processing units (CPU) in a computing architecture.
2. Description of the Related Art
While CPU performance continues to increase rapidly, the performance of the input/output (I/O) bus architecture has lagged significantly. High-resolution, 3D graphics and streaming video are increasing bandwidth demand between micro CPUs and graphics CPUs. A number of new technologies are responsible for the increasing demand for additional bandwidth. The Scalable Link Interface (SLI) is a method developed for linking two or more graphics cards together via parallel processing in order to increase the processing power available for graphics. In SLI graphics schemes, two identical graphics cards are used to control the screen. Typically, each graphics card controls half the screen. With SLI graphics technology, it is possible to roughly double the amount of graphics complexity that can be handled by a computer system with the addition of the second graphics card.
A common requirement to implement SLI graphics schemes is that data processing systems have more than one CPU for optimal performance. Two separate CPUs typically will generate two separate data streams to the two identical graphics cards and transmit to two separate I/O bridges that are directly connected to each CPU generating its half of the graphics traffic. Unfortunately, when a system has a single CPU, SLI support cannot live up to its full potential. Supporting the minimal single CPU system requires a significant sacrifice in SLI graphics performance since all of the I/O would have to be connected to one single CPU in the absence of a second CPU.
Traditionally, to support a multi-CPU SLI scheme, firmware and supporting architecture must be provided specific to the multi-CPU scheme. Newer versions of processors using hypertransport may need two hypertransports between processors in dual processor socket systems to provide adequate memory performance.
By comparison, different firmware and supporting architecture must be provided to support single-CPU scheme, because the infrastructure of the multi-CPU scheme differs from that of the single CPU scheme. Thus, the presence or absence of a multi-CPU scheme must be known a priori at the time of manufacture in order to provide the proper firmware and supporting architecure. Yet, many end-users prefer to purchase a minimal configuration with an option to upgrade from a single-CPU system to a multi-CPU system on one platform. So much, however, is not possible given the disparate firmware and architecture required to support the multi-CPU scenario.